1. Field of the Invention
The present invention relates to a semiconductor memory apparatus. More particularly, the present invention relates to a non-volatile memory.
2. Description of the Related Art
In recent years, a non-volatile memory constituted by non-volatile memory cells having floating gates has been vigorously developed. As shown in FIG. 1, a conventional non-volatile memory is provided with a word line W1, a word line W2, an X-decoder 41, a bit line B1, a bit line B2, output signals Y1, Y2, a sense amplifier 43, an N-channel transistor N1, an N-channel transistor N2, an N-channel transistor N3, an N-channel transistor N4, a P-channel transistor P1 and a P-channel transistor P2.
The word line W1 is connected to the control gates of memory cells MC1, MC2. The word line W2 is connected to the control gates of memory cells MC3, MC4. The X-decoder 41 is connected to the word lines W1, W2. The bit line B1 is connected to drains of the memory cells MC1, MC3. The bit line B2 is connected to drains of the memory cells MC2, MC4. The output signals Y1, Y2 are connected to a Y-decoder 42. The sense amplifier 43 receives a pre-charge signal PRECH. The N-channel transistor N1 is connected to the bit line B1 and the sense amplifier 43, and receives from a gate thereof the output signal Y1. The N-channel transistor N2 is connected to the bit line B2 and the sense amplifier 43, and receives from a gate thereof the output signal Y2. The N-channel transistor N3 is connected to the bit line B1 and a GND power supply, and receives from a gate thereof a discharge signal DIS. The N-channel transistor N4 is connected to the bit line B2 and the GND power supply, and receives from a gate thereof the discharge signal DIS. The P-channel transistor P1 is connected to the bit line B1 and a VDD power supply, and receives from a gate thereof an input signal DW1. And, the P-channel transistor P2 is connected to the bit line B2 and the VDD power supply, and receives from a gate thereof an input signal DW2.
Each of the memory cells MC1 to MC4 is a non-volatile memory cell having the control gate and the floating gate. A threshold of the memory cell is controlled on the basis of an amount of electrons sent to the floating gate.
For example, when the electrons are implanted into the floating gate, its threshold VTM becomes high. For example, it is set to 6 V. Also, if the electrons are drawn out from the floating gate, its threshold VTM becomes low. For example, it is set to 2 V.
Here, if the threshold VTM of the memory cell is high (for example, VTM=6 V) so that the memory cell is sufficiently turned off even when a voltage to read a data stored in the memory cell, for example, 4 V is applied to the word line, it is assumed that a data xe2x80x9c0xe2x80x9d is stored in its memory cell. If the VTM is low (for example, VTM=2 V) so that the memory cell is sufficiently turned on, it is assumed that a data xe2x80x9c1xe2x80x9d is stored in the memory cell.
A write circuit 44 has the P-channel transistors P1, P2. It sets the input signal DW1 or DW2 at a low level at a time of a writing operation, and supplies the VDD power supply through the transistor P1 or P2 to the bit line B1 or B2.
The sense amplifier 43 receives the pre-charge signal PRECH. When its signal becomes at a high level, it supplies 1 V as a pre-charge level to the N-channel transistors N1, N2.
The operation for reading the data stored in the memory cell in this conventional example will be described below with reference to timing charts of FIGS. 2A to 2I.
By the way, let us suppose that the data xe2x80x9c0xe2x80x9d is stored in the memory cells MC1, MC2, and the data xe2x80x9c1xe2x80x9d is stored in the memory cells MC3, MC4. It is assumed to read the data in the memory cell MC1.
At first, the bit lines B1, B2 are discharged (a period ti). So, the output signals Y1, Y2 of the Y-decoder 42 are set to the low level, and the discharge signal DIS is set to the high level. The input signals DW1, DW2 are set to the high level. Thus, the N-channel transistors N1, N2 are turned off. The N-channel transistors N3, N4 are turned on. The P-channel transistors P1, P2 are turned off. And, the bit lines B1, B2 are set to the GND level.
Next, a selected bit line (here, the bit line B1) is pre-charged (a period t2). So, the output signal Y1 is set to the high level, and the output signal Y2 is set to the low level. The pre-charge signal PRECH is set to the high level, and the discharge signal DIS is set to the low level. Thus, the N-channel transistors N2 to N4 are turned off, and the N-channel transistor N1 is turned on. Hence, 1 V implying the pre-charge level is supplied to the bit line B1 through the transistor N1 from the sense amplifier.
Next, a voltage to carry out the reading operation is supplied to a word line (here, the word line W1) of the memory cell to be selected, and a sampling is carried out (a period t3). To do so, the pre-charge signal PRECH is set to the low level. The word lines W1, W2 are switched to the high level (for example, 4 V), and the low level (for example, 0 V), respectively. Thus, 1 V is supplied to the drain of the memory cell MC1, and 4 V is supplied to the control gate. Then, the stored data is sampled. Since the data xe2x80x9c0xe2x80x9d is stored in the memory cell MC1, a current does not flow through the memory cell MC1. Hence, a potential of the bit line is not changed, and it is kept at 1 V. Its level as the data xe2x80x9c0xe2x80x9d is detected by the sense amplifier 43. By the way, if the data xe2x80x9c1xe2x80x9d is stored in the memory cell, the current flows through the memory cell. Hence, the potential of the bit line is changed from 1 V to 0.9 V. Its changed level as the data xe2x80x9c1xe2x80x9d is detected by the sense amplifier 43. The operation for reading the memory cell MC1 is ended after the above-mentioned operations.
In the reading operation, the potential of the bit line is once set to the GND level by the discharge operation. After that, it is pre-charged to 1 V. Thus, when the data xe2x80x9c1xe2x80x9d is sampled, the time required to change the potential of the bit line from 1 V to 0.9 V is reduced to thereby enable the reading operation to be made faster.
However, even in the discharge operation, as the potential of the bit line is higher, it is necessary to make the discharge period longer. Although 4 V is applied to the word line W1 at the time of the sampling of the memory cell MC1, the data xe2x80x9c0xe2x80x9d is stored in the memory cell MC2. So, the memory cell MC2 is at the off-state. For this reason, if a leakage current exists in the P-channel transistor P2 in the write circuit 44, the bit line B2 is charged by the leakage current during the sampling of the memory cell MC1. Thus, there may be a possibility that the potential of the bit line B2 is raised up to a maximum VDD level. Also, since the data stored in the memory cell MC1 is at xe2x80x9c0xe2x80x9d, the memory cell MC1 is at the off-state. Hence, even the bit line B1 is similarly charged by the leakage current, and there may be a possibility that it is raised up to the maximum VDD level.
In order to read the memory cell MC2 after reading the memory cell MC1, the bit line is discharged (a period t4). However, there may be a possibility that the potential of the bit line B2 is equal to or greater than 1 V implying an expectation value (an over-discharge state). Thus, in order to surely discharge the bit line, it is necessary to make the discharge period longer. Hence, the conventional non-volatile memory has the problem of the impediment against the higher speed of the reading operation.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-64289) discloses the following non-volatile memory. In the non-volatile memory containing: a memory cell array in which memory cells arrayed in a form of rows and columns are mounted; and a row decoder having voltage supply transistor circuits for supplying voltages to the control gates of the memory cells when data are written to the memory cells, in which the number of voltage supply transistor circuits corresponds to the number of rows, each of the voltage supply transistor circuits is divided into a plurality of blocks, and the voltage supply ability of the voltage supply transistor circuit in each block can be controlled on the basis of an address given to the row decoder.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-17519) discloses the following output buffer circuit. It is provided with: an output drive buffer driven by an input signal; a transistor connected between an output terminal and an output end of the output drive buffer; a switch for connecting a gate electrode of the transistor to a power supply potential or releasing it therefrom; a control circuit for generating a predetermined control signal from the input signal and outputting from the output end; and a capacitance element connected between the gate electrode and the output end of the control circuit. The control circuit, when the input signal is changed, once turns off the switch, and turns on it after a predetermined period, and charges the capacitance element when it is at the off-state, and inverts a potential of the output end in response to the transition from the off-state to the on-state.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor memory apparatus that can surely attain a discharge operation while reducing a discharge period when a reading operation is done.
Another object of the present invention is to provide a semiconductor memory apparatus that can make a reading operation faster.
In order to achieve an aspect of the present invention, a semiconductor memory apparatus, includes: a plurality of memory cells; and a write circuit performing a writing operation on the memory cell, and wherein a first voltage is supplied to the write circuit when the writing operation is performed on the memory cell, and wherein a second voltage equal to or lower than the first voltage is supplied to the write circuit when a reading operation is performed on the memory cell.
In this case, a semiconductor memory apparatus, includes: a plurality of memory cells connected to a plurality of bit lines; and a write circuit performing a writing operation on the memory cell, and wherein a specific voltage is supplied to the write circuit when a reading operation is performed on the memory cell, the specific voltage being equal to or lower than a voltage of the bit line selected when the reading operation is performed.
In order to achieve another aspect of the present invention, a semiconductor memory apparatus, includes: a plurality of memory cells; a plurality of bit lines connected to the. plurality of memory cells; a write circuit connected to the plurality of bit lines; and an N-channel transistor for connecting a first power supply to the write circuit when a first operation is performed and for connecting a second power supply different from the first power supply to the write circuit when a second operation different from the first operation is performed.
In this case, a first electrode of the N-channel transistor is connected to the write circuit, and a second electrode of the N-channel transistor is connected to a specific power supply, and one of a first voltage corresponding to the first power supply and a second voltage corresponding to the second power supply is supplied to a control electrode of the N-channel transistor.
Also in this case, the N-channel transistor is an N-channel non-doped transistor.
Further in this case, the semiconductor memory apparatus, further includes: a first transistor connected to the first power supply and to the control electrode of the N-channel transistor; and a second transistor connected to the second power supply and to the control electrode of the N-channel transistor.
In this case, the first and second transistors are a same conductive type with each other, and wherein a read signal outputted when a reading operation is performed on the memory cell is supplied to a control electrode of the first transistor, and wherein a reverse signal of the read signal is supplied to a control electrode of the second transistor.
Also in this case, a conductive type of the first transistor is opposite to a conductive type of the second transistor, and wherein a read signal outputted when a reading operation is performed on the memory cell is supplied to control electrodes of the first and second transistors.
Further in this case, the write circuit includes a P channel transistor provided between the N-channel transistor and the bit line.
In this case, the semiconductor memory apparatus, further includes: a first resistor connected between the first power supply and the second transistor; and a second resistor connected between a ground and the second transistor.
Also in this case, the memory cell is a non-volatile memory cell having a floating gate.
Further in this case, a second specific voltage corresponding to the second power supply is equal to or lower than a first specific voltage corresponding to the first power supply.
In this case, the second operation is a reading operation performed on the memory cell, and the first operation is any one of operations other than the reading operation.
Also in this case, the first operation is a writing operation performed on the memory cell.
Further in this case, the first specific voltage is a voltage of the bit line selected when a reading operation is performed on the memory cell.
In this case, the specific voltage is supplied to the write circuit such that the bit line is not charged beyond the specific voltage even if the bit line is charged by a leakage current outputted from the write circuit.
Also in this case, the second power supply includes a third transistor of a conductive type opposite to the conductive type of the first and second transistors connected to the second transistor, and a first unit supplying a third power supply voltage to the third transistor in response to the read signal, and a second unit supplying a voltage higher by a threshold voltage of the third transistor than the second power supply in voltage to a control electrode of the third transistor in response to the read signal.
Further in this case, the second power supply includes a same conductive type of third transistor with the second transistor connected to the second transistor, and a first unit supplying a third power supply voltage to the third transistor in response to the read signal, and a second unit supplying a voltage higher by a threshold voltage of the third transistor than the second power supply in voltage to a control electrode of the third transistor in response to the read signal.
In this case, the semiconductor memory apparatus, further includes: a sense amplifier connected to the plurality of bit lines supplying a read voltage to the plurality of bit lines in case of a first mode and detecting a change of a voltage of the bit line based on whether the memory cell is in a conducting state or a not-conducting state in case of a second mode.
Also in this case, the sense amplifier includes a current mirror circuit sensing a voltage level of the bit line, a third unit outputting the read voltage to the bit line, and a fourth unit activating the current mirror circuit and deactivating the third unit when a pre-charge signal is a first level and deactivating the current mirror circuit and activating the third unit when the pre-charge signal is a second level different from the first level.